High Flexible And Low Latency Memory-Based Fft Architecture

Abstract

A memory-based FFT/DFT processor with high flexibility and low latency is presented in this brief. It is intended for use in next-generation wireless communication systems, including 4G, WLAN, and 5G.The proposed architecture supports 54 transform modes, including FFTs from 16 to 4096 points and DFTs from 12 to 2400 points, through a single processing path. A reconfigurable high-radix butterfly (HRSB) unit enables the efficient execution of multiple radix operations within a single core, significantly reducing the number of computation stages. It eliminates the need for large coefficient ROMs and traditional complex multipliers by performing twiddly factor multiplication using a pipelined CORDIC engine. Memory access conflicts are avoided by using circular address counters and bit-reversed addressing across three banked memory groups.