Congestion Aware Priority-based Routing using On-Chip Memory for NoC Architecture

Abstract

Field Programmable Gate Array (FPGA) involves an array of programmable logic blocks and configurable interconnects which allows users to establish digital circuits and specialized functionality. The Network on Chip (NoC) is a router-based packet-switching network among System on Chip (SoC) modules. However, the node processes incoming data, routes operations, and transmits it to the next node before storing the output in a buffer to avoid congestion. This approach, though effective in managing data flow, increases both area and power consumption. To overcome this problem, the Congestion Aware Priority-based Routing using On-Chip Memory (CAPROCM) is proposed to minimize area and power consumption by removing crossbar switches and Input/Output (I/O) buffers. Initially, the priority encoder determines the priority of the packet and encodes the priority information to an arbiter. The arbiter ensures that the packet with a high priority is processed first. Then, the XY routing process is generated to evaluate the routing path based on the packet’s address. Level-Encoded Dual-Rail (LEDR) is utilized for transferring data and ensures error correction and detection. CAPROCM is evaluated with Look Up Table (LUT), Flip Flop (FF), I/O, Global Buffer (BUFG), Bonded Input/ Output Block (Bonded IOB), Slice registers, and Power. While compared to the existing methods like NoC-based hardware-software co-design model, the proposed CAPROCM achieves better power consumption of 0.324 W for Virtex-7 XC7VX690-3 FPGA device.